is a new of highly integrated, low-power GPS product – based on a 0.13 micron CMOS process of the SiRFstarIII-GSC3f-architecture. It is a single-board solution with increased to 20 parallel channels. The JP18 unit for the first time combines a complete AGPS digital baseband processor, RF front end, 4 Mb ROM and 4 megabits of flash memory in a small size, providing manufacturers of cell phones, PDAs and other portable and wireless devices with a drop-in AGPS solution they can use to deliver real-time location and navigation capabilities in a simpler, smaller design with extended battery life. This unit will deliver exceptional sensitivity, low power consumption and extremely fast time to first fix (TTFF) in a compact, (11 x 11 mm, 22 pin) package. The digital section of the GPS receiver includes a powerful SiRFstarIII core GPS signal processor that handles all the time critical and low latency acquisition, tracking and reacquisition tasks autonomously, and a 50 MHz ARM7TDMI processor designed to run many OEM user applications.